Today's digital electronic circuits typically contain combinational elements as well as one or more sequential devices, such as flip-flops. Moreover, such digital electronic circuits operate by propagating digital signals along signal paths between those combinational elements and sequential devices during the period between successive clock cycles. The failure of a signal, however, to propagate along one or more such signal paths during a clock period or cycle usually gives rise to an error known as a "delay fault."
In the past, delay faults have normally been detected using traditional test methodologies, such as a "stuck-at-fault" test and/or functional test(s). The stuck-at-fault test applies stimuli to the primary inputs of the circuit so as to excite a known response at the node or site of the suspected fault. Should the response differ from the expected response, then a so-called "stuck-at-fault" exists. For example, if a "stuck-at-zero" fault is present, a logic "0" is still observed at the selected node or site, even though a test vector is applied that under normal operating conditions would cause a logic "1" to be present at the node.
Another traditional test methodology for detecting a delay fault is to perform at the rated speed of the circuit a so-called functional test(s). Problems with this test methodology, however, include the use of higher cost automatic test equipment (ATE) supporting multiple-pin functional testing that operates at the rated speed of the circuit. While this test methodology may be useful for detecting some delay faults, it is not, however, well-suited to ensure the testing of critical timing paths which are of primary concern during the operation of the circuit.
Various attempts have been made to establish a more reliable as well as a better suited test methodology for detecting delay faults. One such attempt involves the application of two test vector sets or patterns. The first test vector set applies initialization values to setup the logic values along the selected path necessary to propagate a desired logic transition. The second test vector set then propagates the desired logic transition along the selected path to either a primary output or latch, thereby activating the delay fault. The delay fault effect is then propagated to an observable output. Delay faults can be detected by determining whether the desired logic transition has been propagated from the input latch to the output latch within a predetermined interval. This test methodology is sometimes called a "two-pattern test," and requires that two test vector sets be applied at the rated speed of the circuit.
Today's digital electronic circuits, however, exceed operating speeds of, for example, 100 MHZ. While the above mentioned delay fault test methodology may be implemented with the latest automatic test equipment (ATE) that offer multiple-pin electronics, in many instances the rated operating speed of the circuit will exceed the capability of the ATE. Although testing can indeed be performed at a lower speed, it does not guarantee that the circuit will operate properly at the rated clock speed. One proposed solution is to vary the clock frequency of the circuit during the propagation of the first and second test vector sets. More specifically, the circuit only operates at the rated speed when the desired logic transition is propagated along the desired path to the destination latch or flip-flop. When the desired node or site is initialized with the desired logic values as well as when the captured logic transition is propagated to the primary outputs, the clock is run at a slower frequency or speed. See, U.S. Pat. No. 5,365,528 entitled "Method For Testing Delay Faults in Non-Scan Sequential Circuits," issued to Agrawal et al.; and Chakraborty et al., "Delay Fault Models and Test Generation for Random Logic Sequential Circuits," 29th ACM/IEEE Design Automation Conference (1992), paper no. 10.2, pp 165-72, which are incorporated herein by reference.
This latter solution has been widely accepted and, indeed, has even been used with digital circuits implementing so-called "scan circuitry" to increase its effectiveness. See, for example, Chakraborty et al., "Design For Testability for Path Delay Faults in Sequential Circuits," 30th ACM/IEEE Design Automation Conference (1993), pp. 453-57. Unfortunately, however, some older and/or less expensive automatic test equipment (ATE) may still be unable to apply test vector sets at the slower clock speed and then within the next clock cycle reliably apply test vector sets at the rated clock speed.
Accordingly, what is needed is a cost-effective technique for testing sequential digital circuits for delay faults which lies within the capabilities of older as well as less expensive automatic test equipment (ATE).